The present invention relates to a semiconductor devices and fabrication methods thereof. More specifically, the present invention relates to a semiconductor device having a capacitor and a contact plug in a DRAM (Dynamic Random Access Memory) or the like, and to a manufacturing method thereof. The present invention also relates to MIM capacitor fabrication methods and systems. The present invention also relates to logic-based embedded DRAM devices and manufacturing methods thereof.
In the integrated circuit (IC) industry, manufacturers are currently embedding dynamic random access memory (DRAM) arrays on the same substrate as CPU cores or other logic devices. This technology is being referred to as embedded DRAM (eDRAM). Embedded DRAM generally can provide micro-controller (MCU) and other embedded controllers faster access to larger capacities of on-chip memory at a lower cost than that currently available using conventional embedded static random access memory (SRAM) and/or electrically erasable programmable read only memory (EEPROM).
A semiconductor memory cell, such as a cell for DRAM or embedded DRAM, is mainly composed of transistors and capacitors. Therefore, improvement in the efficiency of such structures tends to lead the direction in which the technology is developing. DRAM is a volatile memory, and the manner in which to store digital signals is generally determined by the charge or discharge of the capacitor in the DRAM. When the power applied to the DRAM is turned off, the data stored in the memory cell completely disappears.
A typical DRAM cell usually includes at least one field effect transistor (FET) and at least one capacitor. The capacitor is used to store the charge (i.e., signals) in the cell of DRAM. If more charges can be stored in the capacitor, the capacitor has less interference when the amplifier senses the data. In recent years, DRAM memory cells have been aggressively miniaturized from generation to generation. Even if the memory cell is minimized, a constant capacitance in the range of 20 fF to 30 fF is needed in the storage capacitor of the cell to store the information.
When the semiconductor enters the deep sub-micron process, the size of the device becomes smaller. For the conventional DRAM structure, this means that the space used by the capacitor becomes smaller. Since computer software is gradually becoming huge, even more memory capacity is required. In the case where it is necessary to have a smaller size of each memory cell with an increased capacity of memory, the conventional method of fabricating the DRAM capacitor must change in order to fulfill the requirements of the trend.
There are two approaches at present for reducing the size of the capacitor (i.e., reducing its footprint, while increasing its memory capacity). One approach involves the selection of a high-dielectric material. The other approach involves increasing the surface area of the capacitor electrodes by utilizing 3-dimensional or vertical structures.
There are two main types of vertical capacitor structures for DRAM. The first type of vertical structure is the deep trench-type, which can be formed by digging out a trench and forming capacitors for electrodes and dielectrics inside the trench. The second type of vertical structure is the stacked-type, which can be formed by depositing a capacitive dielectric layer and a conductive layer in sequence for the capacitor.
When a dielectric material with a relatively high dielectric constant is used in a stacked or trench capacitor, the materials for manufacturing the upper and the bottom electrodes need to be carefully selected in order to enhance the performance of the capacitor (e.g., reducing leakage current, or suppressing interfacial oxide formation, etc.). A structure known as a metal-insulator-metal (MIM) structure possesses a low-interfacial reaction specificity to enhance the performance of the capacitor. Therefore, it has become an important topic of research for the semiconductor capacitor in the future.
The obtainable capacitance of each cell""s storage capacitor tends to decrease due to the level of the miniaturization of the storage cell. On the other hand, the necessary capacitance of the capacitor is almost constant when the storing voltage to be applied across the capacitor is fixed. Therefore, it is necessary for the capacitor to compensate the capacitance decrease due to the miniaturization by, for example, increasing the surface area of the capacitor. This surface area increase has been popularly realized by increasing the roughness of the lower electrode (e.g., or, storage electrode) surface of the capacitor.
In addition to the application of capacitors to DRAM cells, a capacitor is generally one of the most useful of passive components that is commonly integrated with active bipolar or CMOS transistors in modern VLSI devices. Integrated capacitors are commonly fabricated between polysilicon (i.e. PIP capacitors), poly to polycide/metal (i.e. MIS capacitors), or metal-to-metal (i.e. MIM) capacitors. All of these types of capacitors may be planar in nature for process compatibility and simplicity and can also be formed as 3-dimensional structures for reducing footprints.
The MIM capacitor provides superior advantages for mixed-signal/RF applications than other PIP or MIS capacitors. An MIM capacitor is typically fabricated in the BEOL (back-end-of-line) and requires low process temperatures (i.e., less than 450 C.). Therefore, a minimum disturbance of transistor parameters is present. Additionally, MIM capacitors offer excellent linearity and symmetry due to the lack of the so-called depletion effect in the polysilicon layer, which is generally evidenced in PIP or MIS capacitors. MIM capacitors thus are fully compatible with logic processes in BEOL and are preferred for modern mixed-signal or RF applications. Typical MIM capacitors have a dielectric of PE-oxide (e.g., 400A) deposited at a temperature of 450EC or less with a capacitance density of approximately 1 fF/um2 in planar structures.
For increasingly complex mixed-signal and RF applications, the planar MIM capacitor area is limited by chip size parameters. Thus, the present inventors recognize that a need exists to fabricate capacitors having a small footprint (i.e., higher capacitance density). One common technique for raising the capacitance density involves reducing the dielectric thickness at the cost of worsening linearity and promoting higher leakage currents resulting from higher operating fields. Another common technique involves the utilization of high-k materials (e.g., Ta2O5). Implementing such a technique, however, often requires special structures of electrode materials that raise complex process integration issues. Still another common technique of increasing capacitance density involves increasing the effective electrode area by roughening the electrode surface.
Based on the foregoing, the present inventors have concluded that new techniques are needed for increasing capacitance density. The present inventors thus present new techniques and devices thereof for increasing the electrode area of MIM capacitors utilizing spacer formations on planar metal surfaces. Such new fabrication methods are fully compatible with CMOS technology and represent a promising future for system-on-chip (SOC) with signal-mix and RF applications.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor fabrication method and devices thereof.
It is another aspect of the present invention to provide a method for fabricating a MIM capacitor.
It is yet another aspect of the present invention to provide a method and for fabricating an MIM (metal insulator metal) capacitor utilized in an embedded DRAM-based semiconductor device.
It is still a further aspect of the present invention to provide a method for fabricating a low-temperature MIM capacitor for mixed-signal/RF applications.
The above and other aspects of the present invention can thus be achieved as is now described. A method for fabricating an MIM capacitor on a substrate is disclosed herein. A region of the substrate is generally dedicated for use as an electrode area of the MIM capacitor. The electrode area of the MIM capacitor may be increased utilizing at least one spacer formed on an associated planar metal surface, wherein the planar metal surface is generally formed upon the substrate. An increase in a gain factor of the electrode area is thus dependent upon an associated spacer height and particular islands or vias. A roughened surface is thus created for use as a roughened electrode for subsequent capacitor processes. Fabricating spacers made of conducting or non-conducting materials on the associated planar metal surface can create such an electrode. The MIM capacitor formed thereof can be utilized in mixed-signal and RF applications and is fully compatible with COMS logic fabrication processes.
Thus, two novel fabrications methods for forming low-temperatures MIM capacitors with surface roughening are described herein. The first MIM capacitor formation technique disclosed herein, in accordance with a preferred embodiment of the present invention, involves the formation of PE-oxide islands on a metal surface. The PE-oxide islands (i.e., oxide islands) will be removed later and is therefore comprise disposable PE-oxide islands. Spacers of conducting materials (e.g., TiN or TaN) are formed by deposition and etching back techniques about the oxide islands. Such a conducting spacer thus provides a short to the metal surface below. Thereafter, the oxide islands are removed. The metal surface with conducting spacers thus becomes a roughened electrode for subsequent capacitor processes of dielectric deposition and top electrode formation.
The second MIM capacitor formation technique disclosed herein, in accordance with an alternative embodiment of the present invention, involves the formation of vias in the oxide layer on metal. After the vias are filled through spin coating with protection material (e.g., photo-resist, organic ARC, and so forth), then the protection material in-between vias is removed by performing CMP (Chemical Mechanical Polishing) or an etch back operation. Now, the oxide surface is then exposed and the inside of the via is filled with a protecting material. An anisotropic oxide etch can then be performed, which leads to the formation of oxide spacers around the protection material (e.g., photoresist organic ARC) in the vias. Following PR removal and cleaning, the oxide spacers around the prior vias on the metal surface are coated with a thin conduction material (e.g., TiN or TaN) to form a roughened electrode surface. Subsequent capacitor processes may then follow to complete remaining fabrication steps. The area gain factor of the resulting electrode thus depends on the spacer height and dimensions of the formed islands (i.e., for the 1st technique) or vias (i.e., for the 2nd technique).